Various techniques for improving the high-frequency characteristics of bipolar semiconductor devices have been proposed. Most of the techniques are based on the use of a super self-aligned structure, wherein polycrystalline silicon is used as an electrode for contacting the base region. Konaka, S., et al., IEEE Trans. Electron Devices, Vol. ED-33, Apr., 1986, pp. 526-531. Other processes involve polycrystalline silicon contacted emitters, wherein a polycrystalline silicon layer is used to form a self-aligned emitter electrode. Tang, D.D., IEEE Trans. Electron Devices, Vol. ED28, Aug. 1980, pp. 1379-1384. Self-alignment processing techniques allow production of a transistor with smaller areas than is otherwise possible. A reduced transistor area results in a reduced device junction capacitance, which produces improved high-frequency characteristics.
Most prior self-aligned transistor devices have polycrystalline silicon emitters. The use of polycrystalline silicon has certain drawbacks. For example, polycrystalline silicon exhibits increased emitter resistance due to the lower conductivity of polycrystalline silicon compared to monocrystalline silicon.
Another drawback is that polycrystalline silicon emitters exhibit increased emitter resistance due to the presence of an interfacial oxide or other interfacial contaminants which are inadvertently introduced between the poly and monocrystalline films. It is known that silicon quickly grows a native oxide when exposed to ambient air. Even after an oxide etch treatment, a residual oxide film is usually present. Wolstenholme, G.R., et al. Journal Applied Physics, Vol. 61, Jan. 1987, pp. 225-233. Any residual oxide, whether continuous, "balled-up" or broken-up, will impede current flow.
Polycrystalline silicon emitters typically have poor emitter-base voltage matching between transistors. For analog applications, a good base-emitter voltage match between transistors in the same circuit is often necessary. For example, such a match is necessary for operational amplifiers ("OPAMPS"). Variations in the polycrystalline silicon film, due to variability in the poly to monocrystalline interface, causes variable resistance, thus affecting the voltage. Emitter resistance is also a problem for digital applications. Stevens, E.H., Microelectronics Journal, Vol. 14, pp. 15-20 (1983).
Another problem with prior bipolar semiconductor devices is that they exhibit undesirably high emitter-base junction capacitance. Most high-frequency bipolar transistors including polycrystalline silicon contacted devices, typically have a portion of the emitter diffusion located in the monocrystalline base region. The emitter region may be broken-up in a planar or horizontal region which is usually directly under the emitter opening, and is typically defined by a peripheral sidewall. The plane of the emitter region component results in a plane emitter-base junction capacitance which is typically a function of the emitter area. The peripheral emitter component results in a peripheral or sidewall emitter-base junction capacitance which is a function of the emitter perimeter.
For high-frequency transistors such as for RF or microwave applications, the emitter perimeter to emitter area ratio (Ep/Ea) of the device is typically made large in order to minimize any current crowding effects and minimize the base resistance of the transistor. The total emitter area affects the total device current. The narrower the emitter finger, the lower the intrinsic base resistance.
The total emitter-base junction capacitance is a function of the entire emitter surface which forms a P-N (or N-P) junction with the base layer. A large emitter perimeter translates into large peripheral emitter-base components of capacitance, especially since the peripheral component of the emitter is usually cylindrical since the emitter is formed by implantation and/or diffusion.
Emitter-base capacitance affects the input impedance of transistors. It also affects the transition frequency ("f.sub.t ") of bipolar transistors, particularly at low currents, as shown by the following formula in which f.sub.t is the frequency at which the current gain of the transistor becomes unity; V.sub.t is the thermal voltage, typically 0.025 volt at room temperature; I.sub.c is the total collector current of the device; C.sub.je is the total emitter-base junction capacitance, both peripheral and planar; C.sub.jc is the base-collector junction capacitance; and .tau..sub.f is the sum of the internal delay times including base transit time, emitter delay, and collector space charge layer transit time: EQU 1/(2.pi.f.sub.t)=(V.sub.t /I.sub.c)(c.sub.je +C.sub.jc)+.tau..sub.f
The planar area of the emitter is the area where current injection takes place. The emitter's planar area affects the total device current. The larger the emitter area, the greater the injected current for a given emitter-base voltage. For a given device current, the only way of minimizing the emitter-base capacitance, aside from altering doping levels, is to reduce the peripheral or sidewall capacitance.
Most prior microwave silicon bipolar transistors have been fabricated using quasi-self-aligned schemes and are not fully walled. They are interdigitated transistors having multiple base and emitter contact stripes. These devices feature submicron emitter widths. Basawapatna, G., et al., Microwaves and RF, pp. 153-154 (Nov. 1988). The transistor described by Basawapatna is an NEC transistor having 0.6 um contact widths. The emitter is contacted with arsenic doped polycrystalline silicon. The emitter diffusion into the monocrystalline base region is not walled, meaning that the emitter-base junction is effectively composed of a sidewall and planar portions.
In non-walled bipolar transistors, a reduced performance results from lateral base widening effects. At high current densities, the lateral component of current injection becomes significant. Since the current is injected laterally, the effective base width is now wider than the base width directly under the planar emitter region which results in increased base transit time. Van der Ziel, A. et. al., Proceedings of the IEEE, Vol. 54, pp. 411-412 (Mar. 1976).
Fully or partially walled bipolar transistor emitters have been previously described. El-Diwany, et al., Increased Current Gain and Suppression of Peripheral Base Currents in Silicided Self-Aligned Narrow-Width Polysilicon-Emitter Transistors of an Advanced BiCMOS Technology, IEEE Electron Device Letters, Vol. 9, No. 5, pp. 247-249 (May, 1988). De Jong, et al., Electron recombination at the silicided base contact of an advanced self-aligned polysilicon emitter, Proceedings of the IEEE 1988 Bipolar Circuits and Technology Meeting, pp. 202-205, Minneapolis, Minn., (Sept., 1988). However, since the devices disclosed in these references employ polycrystalline silicon to contact the monocrystalline region of the emitter, they tend to exhibit the increased resistance and poor emitter-base voltage matching problems discussed above.
Several of the above mentioned polysilicon emitter devices feature silicided base and emitter contacts. Silicidation results in consumption of the silicon under and next to the deposited and thermally reacted refractory metal. In the case of bipolar transistors, silicidation of the emitter region has certain drawbacks. For shallow emitter junctions, the silicidation of the emitter regions results in a consumption of the actual emitter region which results in reduced current gain due to increased minority carrier injection in the emitter. Also, variations in the uniformity of the silicidation process will result in non-uniform consumption of the silicon in the emitter region which in turn will result in non-uniform transistor current gain. In the polysilicon devices described above, a thick polysilicon film must be used to avoid these drawbacks, at the expense of increased emitter resistance and increased emitter delay time.